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@@ -72,6 +72,25 @@ gates on deployment prereqs the launcher does NOT own:
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3. Preflight is strict: any FAIL → "no services started". So w2 needs BOTH the
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model and the RoCE selection before it serves.
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+## Forum mining (DGPP thread 383406, 107 posts)
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+
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+- **Post #106 (DGPP author, the newest release notes = the HEAD `d9311e72` that
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+ moved past our `3ad63d6b` pin)** adds: **dense Qwen3.8-27B** support, **three
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+ quantization options across Qwen and full GLM-5.3**, `DGPP_NO_SWAP=1` (launch
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+ ranks in a systemd scope that disallows swap — directly relevant to the GB10
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+ unified-memory swap problem), a 1-second decode-gap target (worst mixed-
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+ workload pause 1.8s → 0.5s), and faster long-context GLM prefill. **This is a
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+ strong reason to bump the DGPP pin** (supervised — read the full changelog +
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+ re-bench; the marker keys on `rev`, so a bump cleanly rebuilds).
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+- **Post #73 (community 2x DGPP)**: 2× ASUS GX10, driver 580.173.02, CUDA
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+ 13.0.88, **one ConnectX-7 RoCE lane per node (200G, GID 3) via a switch** —
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+ matches our fabric. Confirms DGPP wants an explicit single-lane selection.
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+- The thread does NOT document the exact `DGPP_ROCE_DEVICES` value syntax (only
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+ `DGPP_NO_SWAP`). The device names come from the preflight output
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+ (`roceP2p1s0f0/f1`, `rocep1s0f0/f1`); the DGPP repo docs/config are the source
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+ of truth for the exact env format. Candidate launcher follow-up: a
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+ `[dgpp].roce_devices` recipe field → emit `DGPP_ROCE_DEVICES` in the `.env`.
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+
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## Not done overnight (deferred, supervised)
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- Ling 572B-fp8 8x lane (689 GB + all 8 Sparks) and Step-5 8x GB10 probe
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