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+# BLOCKED 2026-09-08 (r28 re-test): the r28 tree advanced the DCP+DFlash
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+# boundary logic (fa4720ea) but the drafter still dies — now at
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+# backend selection, not the old C4 assert: the DFlash attention kernel
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+# is BF16-KV-only ("K and V caches must be bfloat16") while the GLM-5.3
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+# engine runs fp8_ds_mla KV (fork default; no per-drafter dtype override
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+# in this tree) -> "No valid attention backend found ... kv_cache_dtype=
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+# fp8_ds_mla, use_mla=False, block_size=256". Fork-side work: teach
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+# DFlashAttention the fp8_ds_mla KV, or add a drafter bf16-KV override.
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+#
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+# DFlash2 re-test on the r28 full stack (2026-09-08, operator: "maybe it
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+# works now"). The 2026-09-06 blocker (C4 parent-page stride assert + FP8-KV
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+# drafter backend rejection) targeted the r27 tree; r28's vLLM carries
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+# fa4720ea "fix(cache): restore GLM boundaries across DCP and DFlash groups"
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+# + the #646 2048/256 page split, so the geometry may now line up.
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+# Recipe = the r27-dflash2 2x shape (deleted at 17a91a9) retargeted:
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+# method "dflash", incoai/GLM-5.3-Flash-DFlash2 draft, k=7, B12X backend,
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+# block-size 256, 10 GiB KV pin (2x profile).
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+#
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+engine = "vllm"
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+name = "GLM-5.3-Flash NVFP4 (r28 img, DFlash2 k=7, 2x re-test)"
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+docker_image = "jovian-judgement:r28-glm53" # full r28 lock via build_profile
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+build_profile = "r28"
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+docker_image_dir = "jovian-judgement"
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+# Required: the clean r12 image follows the solar contract (ENTRYPOINT []
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+# + CMD bash), so the recipe carries the entrypoint (the old day-0-based
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+# r12 image had ["vllm","serve"] baked in, which is why this was absent
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+# until the clean rebuild).
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+entrypoint = ["vllm", "serve"]
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+model = "local-inference-lab/GLM-5.3-Flash-NVFP4"
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+parent_model = "zai-org/GLM-5.3-Flash"
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+required_nodes = 2
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+tensor_parallel_size = 2
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+pipeline_parallel_size = 1
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+distributed_backend = "mp"
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+shm_size = "32gb"
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+
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+args = [
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+ # Stable served name — quant-agnostic (shared across glm53 quants)
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+ "--served-model-name", "glm53",
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+ "--trust-remote-code",
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+ "--distributed-executor-backend", "mp",
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+ # GMU is ONLY a startup guardrail here (KV pool is pinned below): 0.90
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+ # demands 109.46 GiB free on GB10's 121.63 GiB, but driver reserve +
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+ # page cache routinely leave ~108.5 -> flaky
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+ # "Free memory ... less than desired" boot deaths (this was the class
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+ # of the old "54-second death"), and post-crash reruns see ~106.6 GiB.
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+ # 0.82 = 99.7 GiB, below any realistic dip; does NOT change what gets
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+ # allocated (weights ~93 + pinned KV 10 + activations).
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+ "--gpu-memory-utilization", "0.90",
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+ # Pinned 10 GiB KV (≈1.16M tokens) — GMU sizing has no headroom at
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+ # 92.72 GiB weights/node; pinning also keeps warmup off the swap path
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+ "--kv-cache-memory-bytes", "10737418240",
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+ # No --kv-cache-dtype: let the r12 fork pick its default (the explicit
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+ # fp8 / fp8_ds_mla both failed auto-selection on this build).
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+ # The GLM5Next model wires the B12X sparse-MLA backend (sm_120/sm_121)
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+ # when the global backend is B12X (glm5next/nvidia/attention.py:
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+ # _select_sparse_backend); the sm12x auto-priority list never offers it
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+ # (FLASHINFER_MLA_SPARSE_SM120 only supports head 576, not GLM's 512).
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+ "--attention-backend", "B12X",
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+ # pure I/O loader (kept across every config; 171 GB in ~5.5 min vs ~16 NFS)
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+ "--load-format", "instanttensor",
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+ # [R17 FULL-CLUSTER TEST] lil manifest backends (quality gate: hardmode
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+ # must stay ≥88; r12-era this cluster dropped it to 74 — r17 may carry
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+ # the fix through — one boot decides).
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+ "--block-size", "256",
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+ # FINAL BISECT (2026-09-03, hardmode 176pt, r17 img):
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+ # knobs-only 87: d0 c1 24.1, d8192 23.8
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+ # +moe b12x 88: d0 c1 23.5, d8192 26.6 <- SHIP (2 pts d8192)
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+ # +linear b12x 44: W4A4 linear kernel destroys numerics (param-precision 0%)
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+ # +align 88: but d0 c1 18.6 (-5) — perf-negative, dropped
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+ # (all three together = 44-74; the lab needs its private packed package)
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+ "--max-model-len", "524288",
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+ "--max-num-seqs", "16",
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+ "--max-num-batched-tokens", "4096",
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+ "--enable-chunked-prefill",
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+ "--async-scheduling",
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+ "--enable-prefix-caching",
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+ "--disable-custom-all-reduce",
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+ # Their proven boot: no flashinfer autotune, no CuTe-DSL warmup
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+ "--kernel-config", """
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+'{"enable_cutedsl_warmup":false,"enable_flashinfer_autotune":false}'""",
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+ # Built-in MTP draft, 3 tokens (the r12-qualified "mtp:3" mode — their
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+ # x86 numbers: 254 tok/s CC1, 2.37 accept; the checkpoint embeds up to
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+ # 5 via the model-mtp-0000x shards but 3 is the verified depth). This is
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+ # the checkpoint's own MTP head (Glm5NextMTPModel), NOT dspark — dspark
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+ # is the DeepSeek-V4 family's mechanism; GLM's other r12 mode is
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+ # dflash2:7 with a separate trained draft checkpoint.
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+ # The draft model's vllm_config takes its attention backend from the
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+ # SPECULATIVE config, not the global flag (eagle/utils.py:
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+ # _make_eagle_draft_vllm_config) — B12X here mirrors the main model's.
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+ # r18 used draft_model/FLASH_ATTN/kv auto — both rejected on that fork
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+# (FP8-KV-drafter backend check + C4-page stride assert). r27 qualifies
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+# dflash2 upstream (the #646 2048+256 page split is in this tree); the
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+# drafter/depth follow the working aiden GB10 lane (method "dflash").
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+"--speculative-config", """
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+'{"method":"dflash","model":"incoai/GLM-5.3-Flash-DFlash2","num_speculative_tokens":7}'""",
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+ "--language-model-only",
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+ # MTP + CUDA graphs degrades OUTPUT QUALITY on the glm53 day-0 dev build
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+ # (forum #381350/#44, CONFIRMED by A/B bench 2026-08-28: same seed/flags,
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+ # graphs on = 89/100, eager = 92/100; decode unchanged 28.4 t/s @ c1,
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+ # c2 -7%, TTFT +1.6s). The b12x glm52 stack does NOT need this (its
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+ # graphs+MTP combo benches clean at 100/100) — bug is build-specific.
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+ # graphs moved BEFORE tool-call-parser; enforce-eager removed for the
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+ # r17-graphs test (bisect A2 was 88/100 eager; graphs+MTP fix is public
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+ # in r17 refs? verify by bench).
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+ "--tool-call-parser", "glm47",
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+ "--enable-auto-tool-choice",
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+ "--reasoning-parser", "glm45",
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+]
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+archived = true
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+
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+[env]
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+HF_HUB_OFFLINE = "1"
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+# FlashInfer JIT (mxfp8_gemm_cutlass_sm120, ~12 kernels) compiles at first
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+# boot with 12 parallel nvcc jobs -> OOM-killed (code 137) on GB10's
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+# 121 GB unified while the 93 GB weights + 10 GB KV pin are resident.
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+# MAX_JOBS caps ninja parallelism so the JIT fits in the remaining ~20 GB.
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+MAX_JOBS = "2"
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+# NoPE-MLA rope-pad runtime gate (mod baked into the image)
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+VLLM_MLA_NOPE_PAD_ROPE = "1"
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+VLLM_ENGINE_READY_TIMEOUT_S = "3600"
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+# Upstream launch-script env (memory + compile knobs)
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+PYTORCH_CUDA_ALLOC_CONF = "expandable_segments:True"
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+VLLM_USE_AOT_COMPILE = "0"
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+VLLM_USE_STANDALONE_COMPILE = "1"
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+VLLM_USE_FLASHINFER_SAMPLER = "1"
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+VLLM_USE_BREAKABLE_CUDAGRAPH = "0"
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+TORCH_USE_RTLD_GLOBAL = "1"
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+VLLM_NO_USAGE_STATS = "1"
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+
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+# Architecture (aarch64 / sm_121a DGX Spark)
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+TORCH_CUDA_ARCH_LIST = "12.1a"
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+FLASHINFER_CUDA_ARCH_LIST = "12.1f"
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+CUTE_DSL_ARCH = "sm_121a"
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+CMAKE_CUDA_ARCHITECTURES = "121"
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+OMP_NUM_THREADS = "2"
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+
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+[[extra_mounts]]
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+host = "~/sm121-cache/glm53-jit-121f/b12x"
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+container = "/root/.cache/b12x"
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+
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+# JIT caches persist per-node across serves (was: cold /root/.cache per
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+# container -> ~20 min flashinfer/torch recompile every serve). The host
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+# dirs are shared between lanes of the same arch — each cache
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+# self-namespaces by its engine version key internally.
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+[[extra_mounts]]
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+host = "~/sm121-cache/jit-121f/flashinfer"
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+container = "/root/.cache/flashinfer"
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+
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+[[extra_mounts]]
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+host = "~/sm121-cache/jit-121f/torchinductor"
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+container = "/root/.cache/torchinductor"
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+
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+[[extra_mounts]]
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+host = "~/sm121-cache/jit-121f/vllm"
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+container = "/root/.cache/vllm"
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